CSE 493/593University at Buffalo · VLSI Design
Fall 2026

CSE 493/593 · FALL 2026

VLSI design resources

UP NEXT

Lab 1

Getting Started with Cadence Virtuoso

Due09/22

LAB ASSIGNMENTS

Assignments

1 available · 2 locked
01Lab 1CMOS inverter and basic logic gates
02Lab 2Available later in the semester⌑
03Lab 3Available later in the semester⌑

REFERENCE GUIDES

Reference guides

Cadence setupConnect to UB systems and launch VirtuosoVirtuoso tutorialSchematic, simulation, layout, DRC, and LVS
Shared spaceAvailable when the project begins⌑
Pad frame setupAvailable when the project begins⌑